1. Field of the Invention
This invention relates generally to data processing systems and more particularly to data processing systems in which the system architecture permits parallel execution of a plurality of instructions.
During the operation of the data processing system, events can occur within the system that require the execution of an instruction sequence that is outside the explicit activity required for the completion of the currently executing program. When the events are relevant primarily to the currently executing program, the system response typically is to invoke a software program which is executed in the same context as the current program. The notification of such an event is termed an exception. When the event is primarily relevant to other software programs or to the system as a whole, the response must be processed in a system-wide context. The notification of this latter type event is termed an interrupt. This invention relates to a set of exceptions referred to as scalar arithmetic exceptions, vector arithmetic exceptions, scalar memory management exceptions and vector memory management exceptions.
2. Description of the Related Art
In order to achieve high performance in a data processing system, one technique is to provide apparatus for executing a plurality of instructions in parallel (i.e., instructions whose execution overlap in time). However, when one or more of the currently executing instructions results in a memory management exception or an arithmetic exception, such as an integer overflow, exponent overflow or underflow, etc, the determination of the exact location of the instruction that produced the exception can be extremely difficult. In addition, the diversity of possible exception origins complicates the creation of a software environment for efficiently responding to the exceptions.
Computer architectures, such as the DEC VAX data processing systems and the IBM System/370 data processing systems respond to an exception by aborting all instructions that were initiated after the first instruction to signal an exception condition. For a multiplicity of reasons, such as the differences in instruction execution speed, this technique is difficult to implement in the parallel execution of multiple instructions environment.
Other high performance data processing architectures, such as the CDC-7600 data processing system and the Cray-1, Cray-XMP and the Cray-2 data processing systems simply stop executing instructions at a convenient point in the program environment and provide no method for identifying instructions that signalled an exception condition. In addition, these architectures provide no mechanism for synchronizing the instruction execution with an environment created to respond to the identification of an exception.
A need has therefore been felt for m technique to provide a systematic response to the identification of and response to arithmetic exceptions and memory management exceptions in a data processing unit that can have a plurality of instructions in simultaneous execution.